Memory devices for digital computers are made up of many individual memory cells arranged in an array. Each memory cell is adapted to store one bit of information. In the memory cell array, groups of individual memory cells are arranged in columns with the individual cells in each column connected together by two conductors referred to as bit lines. A memory array may include many columns of memory cells, each column including a bit line pair. Also, each memory cell in the array is connected to a conductor referred to as a word line. The memory array includes a number of word lines, each word line commonly connecting memory cells in a row across the different columns. The word lines are used to activate an individual cell in a particular column for a read operation from the cell or a write operation to the cell.
The bit lines associated with a particular memory cell in a memory array are used to write a bit of information to the memory cell. In a write operation, the particular cell in the column is selected using the word line associated with the cell and then a desired charge state representing a bit of information is applied to the bit line pair associated with the selected cell. The charge state comprises a "high" level voltage signal on one bit line and a "low" level voltage signal on the other bit line of the pair. A "high" level voltage signal on one bit line of the pair represents a "1" while the "high" level voltage on the other bit line represents a "0". The memory cell stores the desired bit of data by maintaining a "high" charge state at one node in the memory cell and a "low" charge state at another node in the cell.
A bit of information stored in a memory cell is read from the cell using the bit line pair connected to the cell, a column decoder, and a sense amplifier. The column decoder is connected to each bit line pair in the memory array and operates to select the bit line pair associated with the memory cell from which data is to be read. Before a read operation, the bit lines associated with the desired cell are both pre-charged to a "high" voltage level. In the read operation, the desired memory cell is activated using the word line associated with the cell, and this activation enables the cell to apply the stored charge state to the bit lines associated with the cell. When the charge state stored by the cell is applied to the bit lines, the voltage on one bit line remains at the "high" level voltage while the voltage on the other bit line drifts to a lower voltage level. When a sufficient voltage differential develops between the bit lines, the sense amplifier converts signals on the selected bit lines to digital signals representing the data which was stored by the memory cell.
In order to improve system performance it is desirable to increase the speed at which data may be written to a memory cell and increase the speed at which data may be read from the cell. One factor in the rate at which data may be read from a memory cell is the time required for the minimum voltage differential to develop on the bit lines during a read operation. In order to enhance the speed of a read operation, columns of memory cells may be divided up into segments. Each segment of memory cells may be connected to a local bit line pair. This local bit line pair is connected to a global bit line pair through a suitable boost amplifier. A boost amplifier arrangement is illustrated in U.S. patent application Ser. No. 08/904,987, entitled Bit Line Domino Boost Amplifier, the disclosure of which is hereby incorporated herein by reference.
Another factor in the speed of a read operation is the speed at which a particular bit line pair may be selected by the column decoder. In prior art memory arrays the column decoder arrangement included a plurality of bit switch transistors, each transistor connecting a different bit line to the input of the sense amplifier. The bit switch transistors were used as switches to enable only the desired bit lines to provide an input to the sense amplifier in a particular read operation. In a read operation, biasing signals were applied to the bit switches associated with the two bit lines from which the data was to be read. These biasing signals biased the particular bit switches to a conductive state allowing the charge state of the two bit lines to be applied as the inputs to the sense amplifier. The sense amplifier then operated in response to a sense enable signal to sense the differential voltage state on its inputs and produce the desired digital signal output.
This prior art bit switch arrangement required the memory cell in a read operation not only to drive the voltage on the bit line pair but also drive the voltage signals on the input lines to the sense amplifier. The diffusion capacitance on the bit lines and the inputs to the sense amplifier slowed the rate at which the required differential voltage developed at the sense amplifier inputs and therefore slowed the read operation.